Commit 5705bcee authored by az2lou's avatar az2lou
Browse files

WIP

parent 419b50d0
......@@ -2,24 +2,26 @@
XILINX_TOOL_HOME="${XILINX_TOOL_HOME:-/home/az2lou/Code/xilinx-tools}"
FOLDERS="/home/az2lou/Code/xilinx-tools/output/*"
alias vivado="/opt/Xilinx/Vivado/2018.2/bin/vivado"
echo "design, logic, rent parameter" > results.csv
for f in $FOLDERS
for device in xc7s50 xc7s75 xc7s100
do
design=$(basename $f)
echo $design
FOLDERS="/home/az2lou/Code/xilinx-tools/output/$device/*"
echo "design, logic, rent parameter" > $XILINX_TOOL_HOME/output/$device/results.csv
for f in $FOLDERS
do
design=$(basename $f)
echo $design
cd $f
cd $f
# Rent parameter
p_rent=$(grep "template |" design.txt | tr -s ' ' | cut -d ' ' -f 6)
# Rent parameter
p_rent=$(grep "template |" design.txt | tr -s ' ' | cut -d ' ' -f 6)
# LUTs used
luts=$(grep 'Slice LUTs.\s*\|\s*(\d+)' utilization.txt | tr -s ' ' | cut -d ' ' -f 5)
# LUTs used
luts=$(grep 'Slice LUTs.\s*\|\s*(\d+)' utilization.txt | tr -s ' ' | cut -d ' ' -f 5)
echo "$design, $luts, $p_rent" >> $XILINX_TOOL_HOME/results.csv
echo "$design, $luts, $p_rent" >> $XILINX_TOOL_HOME/output/$device/results.csv
done
done
......@@ -28,10 +28,10 @@ do
cd $XILINX_TOOL_HOME/output/$device/$filename/
# change the device in the tcl script
awk -v device="$device" '/create_project/{$NF=device} 1' syn.tcl > tmp
mv tmp syn.tcl
awk -v device="$device" '/create_project/{$NF=device} 1' impl.tcl > tmp
mv tmp impl.tcl
/opt/Xilinx/Vivado/2018.2/bin/vivado -mode tcl -s syn.tcl
/opt/Xilinx/Vivado/2018.2/bin/vivado -mode tcl -s impl.tcl
done
......
create_project -force proj ./proj -part xc7s100
# set_property board_part www.digilentinc.com:pynq-z1:part0:1.0 [current_project]
create_project -force proj ./proj -part xc7z020clg400-1
add_files [glob *.v]
read_xdc template.xdc
update_compile_order -fileset sources_1
set_property top template [current_fileset]
set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-mode out_of_context} -objects [get_runs synth_1]
launch_runs synth_1 -jobs 4
wait_on_run synth_1
launch_runs impl_1 -jobs 4
wait_on_run impl_1
open_run synth_1 -name synth_1
write_verilog -force -mode funcsim post-synth.v
open_run impl_1 -name impl_1
write_verilog -force -mode timesim -sdf_anno true -sdf_file post-par.sdf post-par.v
write_sdf -force post-par.sdf
if { [ catch {open_run impl_1 -name impl_1} fid] } {
puts stderr "Could not open project\n$fid"
exit 1
}
report_utilization -file utilization.txt
report_design_analysis -complexity -file design.txt
report_timing -file timing.txt
close_project
exit
# report for impl
# open_project proj/proj.xpr
# if { [ catch {open_run impl_1 -name impl_1} fid] } {
# puts stderr "Could not open project\n$fid"
# exit 1
# }
# report_utilization -file utilization.txt
# report_design_analysis -complexity -file design.txt
# report_timing -file timing.txt
# close_project
# exit
create_clock -period 10.000 -waveform {0.000 5.000} [get_nets clk]
create_clock -period 10.000 -waveform {0.000 5.000} [get_nets clock]
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