Commit a74706b4 authored by Anirudh Mohan Kaushik's avatar Anirudh Mohan Kaushik

deadlock fix

parent 244f78ca
#define TRACE 1
#define TRACE 0
#define WB_RANDOM 0
#define READ_WB_RANDOM 0
#define RANDOM_RECV 0
#define WRITE_HITS 0
// BASELINE 1 does not use proposed solution
// BASELINE 0 uses proposed solution
#define NPROC 7
#define NPROC 4
#define BASELINE 0
#define SLOT_WIDTH 50
#define MAX_NPROC 8
......@@ -47,9 +47,9 @@ class SimpleMemory(AbstractMemory):
cxx_header = "mem/simple_mem.hh"
port = SlavePort("Slave ports")
# For 2GHz setup
#latency = Param.Latency('9.5ns', "Request to response latency")
latency = Param.Latency('9.5ns', "Request to response latency")
# For random tester
latency = Param.Latency('22ns', "Request to response latency")
#latency = Param.Latency('22ns', "Request to response latency")
latency_var = Param.Latency('0ns', "Request to response latency variance")
# The memory bandwidth limit default is set to 12.8GB/s which is
# representative of a x64 DDR3-1600 channel.
......
......@@ -1542,23 +1542,23 @@ machine(L1Cache, "MSI Snooping L1 Cache CMP")
// Transition from IS_AD to IS_D
transition(IS_AD, {OWN_GETS, OWN_GETI}, IS_D) {
setFirstScheduledTime;
//l_popRequestQueue;
//setFirstScheduledTime;
l_popRequestQueue;
}
// Transition from IM_AD to IM_D
transition(IM_AD, OWN_GETM, IM_D) {
setFirstScheduledTime;
//l_popRequestQueue;
//setFirstScheduledTime;
l_popRequestQueue;
}
// Transition from IS_D to S
transition(IS_D, Data, S) {
u_writeDataToL1Cache;
r_load_hit;
calcLatencyProfile;
//calcLatencyProfile;
s_deallocateTBE;
//o_popIncomingResponseQueue;
o_popIncomingResponseQueue;
kd_wakeUpDependents;
ka_wakeUpAllDependents;
}
......@@ -1571,9 +1571,9 @@ machine(L1Cache, "MSI Snooping L1 Cache CMP")
transition(IM_D, Data, M) {
u_writeDataToL1Cache;
s_store_hit;
calcLatencyProfile;
//calcLatencyProfile;
s_deallocateTBE;
//o_popIncomingResponseQueue;
o_popIncomingResponseQueue;
kd_wakeUpDependents;
ka_wakeUpAllDependents;
}
......@@ -1594,9 +1594,9 @@ machine(L1Cache, "MSI Snooping L1 Cache CMP")
transition(IS_DI, Data, I) {
u_writeDataToL1Cache;
r_load_hit;
calcLatencyProfile;
//calcLatencyProfile;
s_deallocateTBE;
//o_popIncomingResponseQueue;
o_popIncomingResponseQueue;
ff_deallocateL1CacheBlock;
kd_wakeUpDependents;
ka_wakeUpAllDependents;
......@@ -1640,12 +1640,12 @@ machine(L1Cache, "MSI Snooping L1 Cache CMP")
// Transition from IM_DS to S
transition(IM_DS, Data, MS_A) {
u_writeDataToL1Cache;
calcLatencyProfile;
//calcLatencyProfile;
s_deallocateTBE;
s_store_hit;
bpm_issuePUTMD;
//cc_sendDataCacheToCache;
//o_popIncomingResponseQueue;
o_popIncomingResponseQueue;
}
// Transition from IM_D to IM_DI
......@@ -1662,12 +1662,12 @@ machine(L1Cache, "MSI Snooping L1 Cache CMP")
// Transition from IM_DI to I
transition(IM_DI, Data, MI_A) {
u_writeDataToL1Cache;
calcLatencyProfile;
//calcLatencyProfile;
s_deallocateTBE;
s_store_hit;
bpm_issuePUTMD;
//cc_sendDataCacheToCache;
//o_popIncomingResponseQueue;
o_popIncomingResponseQueue;
}
......@@ -1685,13 +1685,13 @@ machine(L1Cache, "MSI Snooping L1 Cache CMP")
// Transition from IM_DSI to I
transition(IM_DSI, Data, I) {
u_writeDataToL1Cache;
calcLatencyProfile;
//calcLatencyProfile;
s_deallocateTBE;
s_store_hit;
cc_sendDataCacheToDir;
//cc_sendDataCacheToCache;
ff_deallocateL1CacheBlock;
//o_popIncomingResponseQueue;
o_popIncomingResponseQueue;
kd_wakeUpDependents;
ka_wakeUpAllDependents;
}
......@@ -1712,8 +1712,8 @@ machine(L1Cache, "MSI Snooping L1 Cache CMP")
transition(SM_W, OWN_UPG, M) {
sx_store_hit;
setFirstScheduledTimeCE;
//l_popRequestQueue;
//setFirstScheduledTimeCE;
l_popRequestQueue;
kd_wakeUpDependents;
ka_wakeUpAllDependents;
}
......@@ -1738,8 +1738,8 @@ machine(L1Cache, "MSI Snooping L1 Cache CMP")
bm_issueGETMR;
i_allocateTBE;
copyStartTimeCETBE;
setFirstScheduledTime;
//l_popRequestQueue;
//setFirstScheduledTime;
l_popRequestQueue;
}
transition(S, Other_UPG, I) {
......
......@@ -298,7 +298,7 @@ PerfectSwitch::operateVnet(int vnet)
// The value in the comparison should reflect the number of cores + memory
// 6 means, 4 cores with 1 shared L2 and memory
//
if (m_switch_id < 8) {
if (m_switch_id < 5) {
if (incoming != outgoing) {
DPRINTF(RubyNetwork, "Enqueuing net msg from "
"inport[%d][%d] to outport [%d][%d].\n",
......
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