ModuleDecl.cpp 8.05 KB
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#include <string>
#include "ModuleDecl.h"

using namespace scpar;

using std::string;

ModuleDecl::ModuleDecl():
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  _moduleName{"NONE"},
  _classdecl{nullptr} {
  }
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ModuleDecl::ModuleDecl( const string &name, CXXRecordDecl *decl ):
  _moduleName{name},
  _classdecl{decl} {
  }
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ModuleDecl::~ModuleDecl() {
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  // Delete all pointers in ports.
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  for ( auto input_port: _iports ) {
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    // Second is the PortDecl*.
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    delete input_port.second;
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  }
  _iports.clear();

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  for ( auto output_port: _oports ) {
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    // Second is the PortDecl*.
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    delete output_port.second;
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  }
  _oports.clear();

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  for ( auto io_port: _ioports ) {
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    // Second is the PortDecl*.
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    delete io_port.second;
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  }
  _ioports.clear();

}

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void ModuleDecl::setModuleName( const string &name ) {
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  _moduleName = name;
}

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void ModuleDecl::addInstances( vector<string> instanceList ) {
  _instanceList = instanceList;
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}

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void ModuleDecl::addSignalBinding( map<string, string> portSignalMap ) {
  _portSignalMap.insert(portSignalMap.begin(), portSignalMap.end());
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}

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void ModuleDecl::addSignals( FindSignals::signalMapType *signal_map ) {
  for ( auto sit: *signal_map ) {
    string name = sit.first;
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    // It is important to create new objects. 
    // This is because the objects created during Find*
    // may go outside scope, and free up allocated memory.
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    SignalContainer *sc = new SignalContainer(*sit.second);
    Signal *sig = new Signal(name, sc);
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    _signals.insert( ModuleDecl::signalPairType( name, sig ) );
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  }
}

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void ModuleDecl::addInputPorts( FindPorts::PortType p ) {
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  for ( auto mit: p ) {
    string name = mit.first;
    FindTemplateTypes *template_type = new FindTemplateTypes(mit.second);
    PortDecl *pd = new PortDecl( name, template_type );
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    _iports.insert( portPairType( mit.first, pd ) );
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  }
}

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void ModuleDecl::addOutputPorts(FindPorts::PortType p) {
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  for ( auto mit: p ) {
    string n = mit.first;
    FindTemplateTypes *tt = new FindTemplateTypes( mit.second );
    PortDecl *pd = new PortDecl( n, tt );
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    _oports.insert(portPairType(n, pd));
  }
}

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void ModuleDecl::addInputOutputPorts( FindPorts::PortType p ) {
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  for ( auto mit: p ) {
    _ioports.insert(portPairType( mit.first, new PortDecl(mit.first, mit.second ) ) );
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  }
}

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void ModuleDecl::addInputInterfaces( FindTLMInterfaces::interfaceType p ) {
  for ( auto mit: p ) {
    string n = mit.first;
    FindTemplateTypes *tt = new FindTemplateTypes( mit.second );
    InterfaceDecl *pd = new InterfaceDecl( n, tt );
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    _iinterfaces.insert( interfacePairType( mit.first, pd ) );
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  }
}

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void ModuleDecl::addOutputInterfaces( FindTLMInterfaces::interfaceType p ) {
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  for ( auto mit: p ) {
    string name = mit.first;
    FindTemplateTypes *tt = new FindTemplateTypes(*mit.second);
    InterfaceDecl *pd = new InterfaceDecl(name, tt);
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    _ointerfaces.insert(interfacePairType(name, pd));
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  }
}

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void ModuleDecl::addInputOutputInterfaces( FindTLMInterfaces::interfaceType p ) {
  //  for (FindTLMInterfaces::interfaceType::iterator mit = p.begin(), mite = p.end();    mit != mite; mit++) {
  for ( auto mit: p ) {
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    _iointerfaces.insert(interfacePairType
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                         (mit.first, new InterfaceDecl(mit.first, mit.second)));
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  }
}


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void ModuleDecl::addConstructor( Stmt *constructor ) {
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  _constructorStmt = constructor;
}

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void ModuleDecl::addProcess( FindEntryFunctions::entryFunctionVectorType * efv ) {
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  _vef = *efv;
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  for ( unsigned int i = 0; i < efv->size(); ++i ) {
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    EntryFunctionContainer *ef = (*efv)[i];

    // Set the entry name.
    string entryName = ef->_entryName;
    string entryType = "";

    // Set the process type
    switch (ef->_procType) {
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    case PROCESS_TYPE::THREAD: {
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      entryType = "SC_THREAD";
      break;
    }
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    case PROCESS_TYPE::METHOD: {
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      entryType = "SC_METHOD";
      break;
    }
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    case PROCESS_TYPE::CTHREAD: {
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      entryType = "SC_CTHREAD";
      break;
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    }
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    default:{
      entryType = "ERROR";
      break;
    }
 
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      _processes.
        insert(processPairType
               (entryName,
                new ProcessDecl(entryType, entryName, ef->_entryMethodDecl, ef)));
    }
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  }
}

vector<string> ModuleDecl::getInstanceList() {
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  return _instanceList;
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}

vector<EntryFunctionContainer*> ModuleDecl::getEntryFunctionContainer() {
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  return _vef;
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}

int ModuleDecl::getNumInstances() {
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  return _instanceList.size();
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}

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ModuleDecl::processMapType ModuleDecl::getProcessMap() {
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  return _processes;
}

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ModuleDecl::portMapType ModuleDecl::getOPorts() {
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  return _oports;
}

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ModuleDecl::portMapType ModuleDecl::getIPorts() {
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  return _iports;
}

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ModuleDecl::portMapType ModuleDecl::getIOPorts() {
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  return _ioports;
}

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ModuleDecl::interfaceMapType ModuleDecl::getOInterfaces() {
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  return _ointerfaces;
}

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ModuleDecl::interfaceMapType ModuleDecl::getIInterfaces() {
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  return _iinterfaces;
}

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ModuleDecl::interfaceMapType ModuleDecl::getIOInterfaces() {
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  return _iointerfaces;
}


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string ModuleDecl::getName() {
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  return _moduleName;
}

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bool ModuleDecl::isModuleClassDeclNull() {
  return ( _classdecl == nullptr );
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}

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CXXRecordDecl *ModuleDecl::getModuleClassDecl() {
  assert(!( _classdecl == nullptr ));
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  return _classdecl;
}

void ModuleDecl::dumpInstances(raw_ostream & os, int tabn) {

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  if ( _instanceList.empty() ) {
    os << " none \n";
  }

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  for (size_t i = 0; i < _instanceList.size(); i++) {
    os <<_instanceList.at(i)<<" ";
  }
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}

void ModuleDecl::dumpSignalBinding(raw_ostream & os ,int tabn) {
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  if ( _portSignalMap.empty() ) {
    os << " none\n";
    return;
  }

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  for ( auto it: _portSignalMap ) {
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    os <<"\nPort : " <<it.first<<" bound to signal : " <<it.second;
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  }
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}

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void ModuleDecl::dumpProcesses(raw_ostream & os, int tabn) {
  if ( _processes.size() == 0 ) {
    os << "none \n";
  } else {
    for ( auto pit: _processes ) {
      ProcessDecl *pd = pit.second;
      pd->dump(os, tabn);
      os << "\n";
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    }
  }
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  os << "\n";
}
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void ModuleDecl::dumpInterfaces(raw_ostream & os, int tabn) {
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  os << "Input interfaces: " << _iinterfaces.size() << "\n";
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  if (_iinterfaces.size() == 0) {
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    os << " none\n";
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  } else {
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    for ( auto mit: _iinterfaces ) {
      mit.second->dump(os, tabn);
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      os << "\n ";
    }
    os << "\n";
  }

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  os << "Output interfaces: " << _ointerfaces.size() << "\n";
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  if (_ointerfaces.size() == 0) {
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    os << "none \n";
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  } else {
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    for ( auto mit: _ointerfaces ) {
      mit.second->dump(os, tabn);
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      os << "\n ";
    }
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    os << "\n";
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  }

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  os << "Inout interfaces: " << _iointerfaces.size() << "\n";
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  if (_iointerfaces.size() == 0) {
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    os << "none \n";
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  } else {
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    for ( auto mit: _iointerfaces ) {
      mit.second->dump(os, tabn);
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      os << "\n ";
    }
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    os << "\n";
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  }
}

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void ModuleDecl::dumpPorts(raw_ostream & os, int tabn) {
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  os << "Input ports: " << _iports.size();
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  if (_iports.size() == 0) {
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    os << "\n none \n";
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  } else {
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    os << "\n ";
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    for ( auto mit: _iports ) {
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      mit.second->dump(os);
      os << "\n ";
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    }
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    os << "\n";
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  }

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  os << "Output ports: " << _oports.size();
  if ( _oports.size() == 0 ) {
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    os << "\n none \n";
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  } else {
    os << "\n ";
    for ( auto mit: _oports ) {
      mit.second->dump(os, tabn);
      os << "\n";
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    }
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  }
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  os << "Inout ports: " << _ioports.size();
  if ( _ioports.size() == 0 ) {
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    os << "\n none \n";
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  } else {
    os << "\n ";
    for ( auto mit: _oports ) {
      mit.second->dump(os, tabn);
      os << "\n ";
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    }
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  }
  os << "\n";
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}

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void ModuleDecl::dumpSignals( raw_ostream & os, int tabn ) {
  if ( _signals.size() == 0 ) {
    os << "none \n";
  } else {
    for ( auto sit: _signals ) {
      Signal *s = sit.second;
      s->dump(os, tabn);
      os << "\n";
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    }
  }
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  os << "\n";
}
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void ModuleDecl::dump(raw_ostream & os) {
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  //  os << "ModuleDecl " << this << " " << _moduleName
  //     << " CXXRecordDecl " << _classdecl << "\n";
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  os << "\n";
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  os << "# Port Declaration:\n";
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  dumpPorts(os, 4);
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  os << "# Signal Declaration:\n";
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  dumpSignals(os, 4);
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  os << "# Processes:\n";
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  dumpProcesses(os, 4);
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  os <<"# Instances:\n";
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  dumpInstances(os, 4);
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  os <<"# Signal binding:\n";
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  dumpSignalBinding(os, 4);
  os << "\n=======================================================\n";
}