Skip to content

GitLab

Commit b6ec3ffa authored by rmrf's avatar rmrf
Browse files

Clearly print which module is not found (For LLNL).

parent 2d556e5f
Hide whitespace changes
Inline Side-by-side
Showing with 270 additions and 303 deletions
src/FindEntryFunctions.h
View file @ b6ec3ffa
......@@ -8,6 +8,7 @@
#include "clang/AST/RecursiveASTVisitor.h"
#include "EntryFunctionContainer.h"
#include <map>
namespace scpar {
using namespace clang;
......@@ -55,7 +56,7 @@ namespace scpar {
entryFunctionVectorType entry_function_list_;
entryFunctionLHSMapType entry_function_map_;
vector< CXXMethodDecl * > other_function_list_;
// Disallow constructor with no argument
FindEntryFunctions( llvm::raw_ostream &os );
......
src/FindNetlist.cpp
View file @ b6ec3ffa
#include "FindNetlist.h"
using namespace scpar;
FindNetlist::FindNetlist(FunctionDecl * fnDecl):
_pass(1)
{
FindNetlist::FindNetlist(FunctionDecl * fnDecl) :
_pass{1} {
TraverseDecl(fnDecl);
_pass = 2;
}
FindNetlist::~FindNetlist()
{
_instanceModuleMap.clear();
_portSignalMap.clear();
_instancePortSignalMap.clear();
FindNetlist::~FindNetlist() {
_instanceModuleMap.clear();
_portSignalMap.clear();
_instancePortSignalMap.clear();
}
FindNetlist::FindNetlist(const FindNetlist &f) {
_pass = f._pass;
_instanceModuleMap = f._instanceModuleMap;
_portSignalMap = f._portSignalMap;
_instancePortSignalMap = f._instancePortSignalMap;
_instanceListModuleMap = f._instanceListModuleMap;
FindNetlist::FindNetlist( const FindNetlist &f ) {
_pass = f._pass;
_instanceModuleMap = f._instanceModuleMap;
_portSignalMap = f._portSignalMap;
_instancePortSignalMap = f._instancePortSignalMap;
_instanceListModuleMap = f._instanceListModuleMap;
}
void FindNetlist::updateInstanceListModuleMap(string instanceName, string moduleName) {
void FindNetlist::updateInstanceListModuleMap( string instanceName, string moduleName ) {
if (_instanceListModuleMap.find(moduleName) == _instanceListModuleMap.end()) {
vector<string> instanceList;
instanceList.push_back(instanceName);
_instanceListModuleMap.insert(instanceListModulePairType(moduleName, instanceList));
}
else {
_instanceListModuleMap.insert(instanceListModulePairType(moduleName, instanceList));
} else {
instanceListModuleMapType::iterator instanceListModuleMapFound = _instanceListModuleMap.find(moduleName);
vector<string> instanceList = instanceListModuleMapFound->second;
instanceList.push_back(instanceName);
......@@ -41,9 +36,8 @@ void FindNetlist::updateInstanceListModuleMap(string instanceName, string module
_instanceListModuleMap.insert(instanceListModulePairType(moduleName, instanceList));
}
}
bool FindNetlist::VisitCXXOperatorCallExpr(CXXOperatorCallExpr * ce)
{
bool FindNetlist::VisitCXXOperatorCallExpr( CXXOperatorCallExpr *ce ) {
bool foundME = false;
......@@ -53,59 +47,59 @@ bool FindNetlist::VisitCXXOperatorCallExpr(CXXOperatorCallExpr * ce)
string signalName;
for (Stmt::child_iterator it = ce->IgnoreImpCasts()->child_begin(), eit =
ce->IgnoreImpCasts()->child_end(); it != eit; it++)
{
if (Expr * e = dyn_cast < Expr > (*it))
{
if (MemberExpr * me =
dyn_cast < MemberExpr > (e->IgnoreImpCasts()))
{
if (DeclRefExpr * de =
dyn_cast < DeclRefExpr > (me->getBase()->IgnoreImpCasts()))
{
moduleName =
de->getDecl()->getType().getBaseTypeIdentifier()->
getName();
instanceName = de->getFoundDecl()->getNameAsString();
}
portName = me->getMemberDecl()->getNameAsString();
foundME = true;
}
if (DeclRefExpr * de =
dyn_cast < DeclRefExpr > (e->IgnoreImpCasts()))
{
if (foundME)
{
signalName = de->getNameInfo().getAsString();
foundME = false;
}
}
}
}
ce->IgnoreImpCasts()->child_end(); it != eit; it++)
{
if (Expr * e = dyn_cast < Expr > (*it))
{
if (MemberExpr * me =
dyn_cast < MemberExpr > (e->IgnoreImpCasts()))
{
if (DeclRefExpr * de =
dyn_cast < DeclRefExpr > (me->getBase()->IgnoreImpCasts()))
{
moduleName =
de->getDecl()->getType().getBaseTypeIdentifier()->
getName();
instanceName = de->getFoundDecl()->getNameAsString();
}
portName = me->getMemberDecl()->getNameAsString();
foundME = true;
}
if (DeclRefExpr * de =
dyn_cast < DeclRefExpr > (e->IgnoreImpCasts()))
{
if (foundME)
{
signalName = de->getNameInfo().getAsString();
foundME = false;
}
}
}
}
if (_instanceModuleMap.find(instanceName) == _instanceModuleMap.end())
{
_instanceModuleMap.
insert(instanceModulePairType(instanceName, moduleName));
_portSignalMap.clear();
updateInstanceListModuleMap(instanceName, moduleName);
}
{
_instanceModuleMap.
insert(instanceModulePairType(instanceName, moduleName));
_portSignalMap.clear();
updateInstanceListModuleMap(instanceName, moduleName);
}
_portSignalMap.insert(portSignalPairType(portName, signalName));
if (_instancePortSignalMap.find(instanceName) ==
_instancePortSignalMap.end())
{
_instancePortSignalMap.
insert(instancePortSignalPairType(instanceName, _portSignalMap));
}
_instancePortSignalMap.end())
{
_instancePortSignalMap.
insert(instancePortSignalPairType(instanceName, _portSignalMap));
}
else
{
_instancePortSignalMap.erase(instanceName);
_instancePortSignalMap.
insert(instancePortSignalPairType(instanceName, _portSignalMap));
}
{
_instancePortSignalMap.erase(instanceName);
_instancePortSignalMap.
insert(instancePortSignalPairType(instanceName, _portSignalMap));
}
return true;
}
......@@ -113,22 +107,22 @@ bool FindNetlist::VisitCXXOperatorCallExpr(CXXOperatorCallExpr * ce)
int FindNetlist::getNumInstances(string moduleName) {
int counter = 0;
for (instanceModuleMapType::iterator it = _instanceModuleMap.begin(), eit = _instanceModuleMap.end();
it != eit;
it++) {
string modName = it->second;
if (modName == moduleName) {
counter++;
}
}
it != eit;
it++) {
string modName = it->second;
if (modName == moduleName) {
counter++;
}
}
return counter;
}
FindNetlist::portSignalMapType FindNetlist::getPortSignalMap() {
return _portSignalMap;
return _portSignalMap;
}
FindNetlist::instanceListModuleMapType FindNetlist::getInstanceListModuleMap() {
return _instanceListModuleMap;
return _instanceListModuleMap;
}
FindNetlist::instanceModuleMapType FindNetlist::getInstanceModuleMap()
......@@ -141,35 +135,25 @@ FindNetlist::instancePortSignalMapType FindNetlist::getInstancePortSignalMap()
return _instancePortSignalMap;
}
void FindNetlist::dump()
{
void FindNetlist::dump() {
llvm::errs() << "\n ----------------- Netlist dump ----------------- \n";
for (instanceModuleMapType::iterator it = _instanceModuleMap.begin(), eit =
_instanceModuleMap.end(); it != eit; it++)
{
llvm::errs() << "\n Instance Name : " << it->first << " Module Name : " << it->
second;
for (instanceModuleMapType::iterator it = _instanceModuleMap.begin(), eit =
_instanceModuleMap.end(); it != eit; it++) {
llvm::errs() << "\n Instance Name : " << it->first << " Module Name : "
<< it->second;
string instanceName = it->first;
if (_instancePortSignalMap.find(instanceName) !=
_instancePortSignalMap.end())
{
instancePortSignalMapType::iterator instancePortSignalMapFound =
_instancePortSignalMap.find(instanceName);
portSignalMapType portSignalMap =
instancePortSignalMapFound->second;
for (portSignalMapType::iterator pit =
portSignalMap.begin(), pite = portSignalMap.end();
pit != pite; pit++)
{
llvm::errs() << "\n Port : " << pit->
first << " ------> " << pit->second;
}
}
else
{
llvm::errs() << "\n No instance name found ////// weird.";
}
llvm::errs() << "\n ------------------------------------------------------\n";
if (_instancePortSignalMap.find(instanceName) != _instancePortSignalMap.end()) {
instancePortSignalMapType::iterator instancePortSignalMapFound =_instancePortSignalMap.find(instanceName);
portSignalMapType portSignalMap = instancePortSignalMapFound->second;
for (portSignalMapType::iterator pit = portSignalMap.begin(), pite = portSignalMap.end();
pit != pite; pit++) {
llvm::errs() << "\n Port : " << pit->first << " ------> " << pit->second;
}
} else {
llvm::errs() << "\n No instance name found ////// weird.";
}
llvm::errs() << "\n ------------------------------------------------------\n";
}
}
src/FindNetlist.h
View file @ b6ec3ffa
......@@ -13,43 +13,43 @@ namespace scpar {
class FindNetlist : public RecursiveASTVisitor < FindNetlist > {
public:
// Removed Model::moduleMapType from constructor
// Have to think of a way to include building
// netlist from module constructors. Right now I am not
// doing it.
FindNetlist(FunctionDecl *);
FindNetlist(const FindNetlist &);
virtual ~FindNetlist();
// Have to think of a way to include building
// netlist from module constructors. Right now I am not
// doing it.
FindNetlist(FunctionDecl *);
FindNetlist(const FindNetlist &);
virtual ~FindNetlist();
public:
typedef pair <string, string> instanceModulePairType;
typedef map <string, string> instanceModuleMapType;
typedef pair <string, string> instanceModulePairType;
typedef map <string, string> instanceModuleMapType;
typedef pair <string, string> portSignalPairType;
typedef map <string, string> portSignalMapType;
typedef pair <string, string> portSignalPairType;
typedef map <string, string> portSignalMapType;
typedef pair<string, portSignalMapType> instancePortSignalPairType;
typedef map<string, portSignalMapType> instancePortSignalMapType;
typedef pair<string, portSignalMapType> instancePortSignalPairType;
typedef map<string, portSignalMapType> instancePortSignalMapType;
typedef pair<string, vector<string> > instanceListModulePairType;
typedef map <string, vector<string> > instanceListModuleMapType;
typedef pair<string, vector<string> > instanceListModulePairType;
typedef map <string, vector<string> > instanceListModuleMapType;
virtual bool VisitCXXOperatorCallExpr (CXXOperatorCallExpr *ce);
virtual bool VisitCXXOperatorCallExpr(CXXOperatorCallExpr *ce);
void updateInstanceListModuleMap(string, string);
void updateInstanceListModuleMap(string, string);
instanceModuleMapType getInstanceModuleMap();
instancePortSignalMapType getInstancePortSignalMap();
instanceListModuleMapType getInstanceListModuleMap();
portSignalMapType getPortSignalMap();
int getNumInstances(string);
void dump ();
instanceModuleMapType getInstanceModuleMap();
instancePortSignalMapType getInstancePortSignalMap();
instanceListModuleMapType getInstanceListModuleMap();
portSignalMapType getPortSignalMap();
int getNumInstances(string);
void dump();
private:
int _pass;
private:
int _pass;
instanceModuleMapType _instanceModuleMap;
portSignalMapType _portSignalMap;
instancePortSignalMapType _instancePortSignalMap;
instanceListModuleMapType _instanceListModuleMap;
};
};
}
#endif
src/Model.cpp
View file @ b6ec3ffa
......@@ -4,13 +4,11 @@
using namespace scpar;
using namespace std;
Model::Model()
{
Model::Model() {
}
Model::~Model()
{
Model::~Model() {
llvm::errs() << "\n[[ Destructor Model ]]\n";
// Delete all ModuleDecl pointers.
for (Model::moduleMapType::iterator mit = _modules.begin();
......@@ -18,17 +16,15 @@ Model::~Model()
// Second is the ModuleDecl type.
delete mit->second;
}
_modules.clear();
_modules.clear();
}
Model::Model(const Model & from)
{
Model::Model(const Model & from) {
_modules = from._modules;
}
void Model::addModuleDecl(ModuleDecl * md)
{
void Model::addModuleDecl(ModuleDecl * md) {
_modules.insert(Model::modulePairType(md->getName(), md));
}
......@@ -36,8 +32,7 @@ void Model::addModuleDeclInstances(ModuleDecl* md, vector<ModuleDecl*> mdVec){
_moduleInstanceMap.insert(moduleInstancePairType(md, mdVec));
}
void Model::addSimulationTime(FindSimTime::simulationTimeMapType simTime)
{
void Model::addSimulationTime(FindSimTime::simulationTimeMapType simTime) {
_simTime = simTime;
}
......@@ -63,43 +58,48 @@ void Model::addSCMain(FunctionDecl *fnDecl){
_scmainFcDecl = fnDecl;
}
void Model::addNetlist(FindNetlist &n) {
void Model::addNetlist( FindNetlist &n ) {
_instanceModuleMap = n.getInstanceModuleMap();
_portSignalMap = n.getPortSignalMap();
_instancePortSignalMap = n.getInstancePortSignalMap();
_instanceListModuleMap = n.getInstanceListModuleMap();
updateModuleDecl();
}
void Model::updateModuleDecl() {
for (moduleMapType::iterator it = _modules.begin(), eit = _modules.end();
it != eit;
it++) {
it != eit; it++) {
string moduleName = it->first;
ModuleDecl* md = it->second;
ModuleDecl *md = it->second;
vector<string> instanceList;
if (_instanceListModuleMap.find(moduleName) != _instanceListModuleMap.end()) {
llvm::errs() << "Finding instances for " << moduleName << " declaration: ";
if ( _instanceListModuleMap.find(moduleName) != _instanceListModuleMap.end() ) {
FindNetlist::instanceListModuleMapType::iterator instanceListModuleMapFind = _instanceListModuleMap.find(moduleName);
md->addInstances(instanceListModuleMapFind->second);
md->addInstances(instanceListModuleMapFind->second);
// Print the names of all the instances
for ( auto instance : instanceListModuleMapFind->second ) {
llvm::errs() << instance << " ";
}
llvm::errs() << "\n";
for (size_t i = 0 ; i < instanceListModuleMapFind->second.size(); i++) {
if (_instancePortSignalMap.find(instanceListModuleMapFind->second.at(i)) != _instancePortSignalMap.end()) {
FindNetlist::instancePortSignalMapType::iterator portSignalMapFound = _instancePortSignalMap.find(instanceListModuleMapFind->second.at(i));
FindNetlist::portSignalMapType portSignalMap = portSignalMapFound->second;
md->addSignalBinding(portSignalMap);
}
else {
llvm::errs() <<"\n Could not find instance and signal";
}
if (_instancePortSignalMap.find(instanceListModuleMapFind->second.at(i)) != _instancePortSignalMap.end()) {
FindNetlist::instancePortSignalMapType::iterator portSignalMapFound = _instancePortSignalMap.find(instanceListModuleMapFind->second.at(i));
FindNetlist::portSignalMapType portSignalMap = portSignalMapFound->second;
md->addSignalBinding(portSignalMap);
} else {
llvm::errs() <<"\n Could not find instance and signal";
}
}
} else {
llvm::errs() <<"NONE.";
}
else {
llvm::errs() <<"\n ERROR: Could not find module";
}
}
}
}
void Model::addSCModules(SCModules * m)
......@@ -141,16 +141,16 @@ void Model::dump(raw_ostream & os)
// int counterModel = 0;
os << "\nNumber of Models : " << _modules.size();
os << "\nNumber of modules : " << _modules.size();
for (Model::moduleMapType::iterator mit = _modules.begin();
mit != _modules.end(); mit++) {
// Second is the ModuleDecl type.
os << "\nModel " << mit->first<<"\n";
os << "\n# Module " << mit->first;
vector<ModuleDecl*> instanceVec = _moduleInstanceMap[mit->second];
for (size_t i = 0; i < instanceVec.size(); i++) {
os <<"\n Instance : "<<i + 1;
os <<", instance: " << i + 1 << " ";
instanceVec.at(i)->dump(os);
}
}
......
src/ModuleDecl.cpp
View file @ b6ec3ffa
......@@ -220,6 +220,10 @@ CXXRecordDecl *ModuleDecl::getModuleClassDecl() {
void ModuleDecl::dumpInstances(raw_ostream & os, int tabn) {
if ( _instanceList.empty() ) {
os << " none \n";
}
for (size_t i = 0; i < _instanceList.size(); i++) {
os <<_instanceList.at(i)<<" ";
}
......@@ -227,32 +231,29 @@ void ModuleDecl::dumpInstances(raw_ostream & os, int tabn) {
void ModuleDecl::dumpSignalBinding(raw_ostream & os ,int tabn) {
for ( auto it: _portSignalMap ) {
os <<"\n Port : " <<it.first<<" bound to signal : " <<it.second;
os <<"\nPort : " <<it.first<<" bound to signal : " <<it.second;
}
}
void ModuleDecl::dumpProcesses(raw_ostream & os, int tabn) {
if (_processes.size() == 0) {
os << " <<<NULL>>>\n";
} else {
for ( auto pit: _processes ) {
ProcessDecl *pd = pit.second;
pd->dump(os, tabn);
os << "\n";
}
void ModuleDecl::dumpProcesses(raw_ostream & os, int tabn) {
if ( _processes.size() == 0 ) {
os << "none \n";
} else {
for ( auto pit: _processes ) {
ProcessDecl *pd = pit.second;
pd->dump(os, tabn);
os << "\n";
}
os << "\n";
}
os << "\n";
}
void ModuleDecl::dumpInterfaces(raw_ostream & os, int tabn) {
for ( auto i = 0; i < tabn; ++i ) {
os << " ";
}
os << "Input interfaces:\n ";
os << "+ Input interfaces:\n ";
if (_iinterfaces.size() == 0) {
os << " <<<NULL>>>\n";
os << " none\n";
} else {
for ( auto mit: _iinterfaces ) {
mit.second->dump(os, tabn);
......@@ -261,112 +262,94 @@ void ModuleDecl::dumpInterfaces(raw_ostream & os, int tabn) {
os << "\n";
}
for ( auto i = 0; i < tabn; ++i ) {
os << " ";
}
os << "Output interfaces:\n ";
os << "+ Output interfaces:\n ";
if (_ointerfaces.size() == 0) {
os << " <<<NULL>>>\n";
os << "none \n";
} else {
for ( auto mit: _ointerfaces ) {
mit.second->dump(os, tabn);
os << "\n ";
os << "\n";
}
os << "\n";
}
for ( auto i = 0; i < tabn; ++i ) {
os << " ";
}
os << "Inout interfaces:\n ";
os << "+ Inout interfaces: ";
if (_iointerfaces.size() == 0) {
os << " <<<NULL>>>\n";
os << "none \n";
} else {
for ( auto mit: _iointerfaces ) {
mit.second->dump(os, tabn);
os << "\n ";
}
os << "\n";
}
os << "\n";
}
void ModuleDecl::dumpPorts(raw_ostream & os, int tabn) {
for ( auto i = 0; i < tabn; ++i ) {
os << " ";
}
os << "Input ports:\n ";
os << "Input ports: " << _iports.size();
if (_iports.size() == 0) {
os << " <<<NULL>>>\n";
os << " none \n";
} else {
os << "\n ";
for ( auto mit: _iports ) {
os << "Print Port\n" << mit.first << "\n";
mit.second->dump(os, tabn);
os << "End print\n";
os << "\n ";
mit.second->dump(os);
os << "\n ";
}
os << "\n";
os << "\n";
}
for ( auto i = 0; i < tabn; ++i ) {
os << " ";
}
os << "Output ports:\n ";
if (_oports.size() == 0) {
os << " <<<NULL>>>\n";
} else {
for ( auto mit: _oports ) {
mit.second->dump(os, tabn);
os << "\n ";
os << "\n";
}
os << "Output ports: " << _oports.size();
if ( _oports.size() == 0 ) {
os << " none \n";
} else {
os << "\n ";
for ( auto mit: _oports ) {
mit.second->dump(os, tabn);
os << "\n";
}