Lab manual for ECE327. Hands-on manual for different CAD tools (Modelsim for RTL simulation, Vivado For FPGA Implementation + Floorplanning) tools. Also includes an operation manual for Xilinx FPGA Pynq board.

  • Hands-on guide to using Modelsim simulation tool for Verilog designs. Includes FPGA-specific features for modelling hard blocks in devices and extracting activity traces for accurate power estimation later.

  • Guide to Xilinx Vivado synthesis and implementation toolflow. Once you have simulated your RTL design, you will implement that on the FPGA board. This requires a compilation process (synthesis) and mapping process (placement + routing).

  • Steps for configuring your own Docker image for ECE327 labs. This is not required and you are able to do everything on eceubuntu.uwaterloo.ca. In case you are keen to setup your own build environment on your own machines, this should be handy.

  • Manuals for mapping Verilog code to the Pynq FPGA board with streaming input + output interfaces. Guides to debugging inside the FPGA during execution. Admin support for setting up your own board.

  • Hands-on manual for explicit floorplanning of FPGA designs. Regular layouts can be specified as geometric patterns on the hardware by the programmer instead of relying on automatic FPGA placement by Vivado. Often results in faster, compact design.