327 lectures


ECE327 lecture slides organized by topic and split into sub-lectures as appropriate. All content taught in the lectures will be tested on the exam. For an idea of what sort of questions are asked, please look at the tutorials.

  • Introduction to ECE327.

    Motivation for studying hardware design. What will you be able to do by end of class. How will be run the class, policies
  • Understand parallelism and concurrency needs for hardware modeling. Simulation semantics of Verilog. Drawing timing diagrams, and basic introduction to Modelsim.

  • Hardware synthesis of digital circuits from RTL descriptions. Differences over traditional software design. Understanding how hardware is generated from RTL code. Arithmetic circuits like adders and multipliers. Matrix Multiplication example.

  • A closer look at top-down synthesis of matrix multiplication hardware blocks. We consider two design alternatives (1) reduction trees, (2) systolic arrays and show how to describe them in RTL.

  • State machines are computational structures for control and management function. They can be used to implement handshaking, control of shared resources, and timing. We will look at RTL formulations for precise state machine design.

  • Extended discussion of state machines. Their use in FSM + Datapath design pattern. Case studies for exotic uses of FSMs.

  • Static scheduling of hardware Datapaths. Template for resource sharing hardware operators, registers, and I/Os. Scheduling table design, minimization, and simplification of hardware required.

  • Advanced memory structures. Multiple ports to the RAM. FIFOs, and Shift Registers. Scheduling RAMs and Datapaths with unrolling and software pipelining optimizations.

  • Introduction to on-chip SRAM memory blocks. RTL description of memory blocks. Inferring memories. Scheduling with memories.

  • Examples of scheduling hardware Datapaths with varying resource constraints. Area-Time tradeoffs. Examples of scheduling DSP blocks.

  • Retiming of Datapaths. Simple rules to move registers around without affecting correctness. C-slow retiming of feedback loops. Vivado example of automated retiming.

  • Pipelining of hardware Datapaths. Basics of pipelining CPUs, and translating terminology to custom datapaths. Analyze latency and throughput properties of pipelined hardware, timing diagrams of such hardware.