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A closer look at top-down synthesis of matrix multiplication hardware blocks. We consider two design alternatives (1) reduction trees, (2) systolic arrays and show how to describe them in RTL.
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Understand parallelism and concurrency needs for hardware modeling. Simulation semantics of Verilog. Drawing timing diagrams, and basic introduction to Modelsim.
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Hardware synthesis of digital circuits from RTL descriptions. Differences over traditional software design. Understanding how hardware is generated from RTL code. Arithmetic circuits like adders and multipliers. Matrix Multiplication example.
