Commit 1624c46c authored by Harry Chan's avatar Harry Chan
Browse files

re organize heading

parent 3868ab4f
......@@ -6,7 +6,7 @@ We provide a fast optimization algorithm and a step-to-step guide on how to gene
> [**"Partitioning FPGA-Optimized Systolic Arrays for Fun and Profit"**](https://git.uwaterloo.ca/watcag-public/fpga-syspart/blob/master/optimization_algo/paper/PID6211513.pdf),
> 2019 International Conference on Field-Programmable Technology
### TODO
## TODO
- [x] Add a public link to the paper
- [x] Basic Demo Flow
- [] Step-by-step guide on
......@@ -16,7 +16,7 @@ We provide a fast optimization algorithm and a step-to-step guide on how to gene
- [] Changes done to ScaleSim
- [] Explanation of the testing result
### Demos
## Demo
The following demos use pre-generated datasets and topologies that can be found in:
- [topologies](https://git.uwaterloo.ca/watcag-public/fpga-syspart/blob/master/optimization_algo/topologies/) contains all the topologies descriping their respective CNN structures
......@@ -61,22 +61,22 @@ To get optimization result with
Result of the optimization will be added to the corresponding csv file under this [folder](https://git.uwaterloo.ca/watcag-public/fpga-syspart/blob/master/optimization_algo/resulting_csv)
### Step-by-step detail guide
## Step-by-step detail guide
#### Custom topologies
### Custom topologies
### Custom target board
#### Custom target board
### Generate data source using SCALE-sim
### Repo breakdown
### Running script targeting specific approach
### Changes made to Scale-sim
## Repo Breakdown
### Interpretation to the test result
## Scale-sim change
## License
This tool is distributed under MIT license.
Copyright (c) 2019 Long Chung Chan, Gurshaant Singh Malik, Nachiket Kapre
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