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watcag-public
fpga-syspart
Commits
591c1377
Commit
591c1377
authored
Feb 14, 2020
by
harrychan
Browse files
added new size
parent
7bf04590
Changes
1
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scaleSim/scale.py
scaleSim/scale.py
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scaleSim/scale.py
View file @
591c1377
...
...
@@ -267,6 +267,8 @@ class scale:
if
self
.
res_enough
((
k
*
3
,
i
)):
all_arr_dim_list
.
append
((
k
*
3
,
i
))
# print(len(all_arr_dim_list))
# print(all_arr_dim_list)
pool
=
Pool
(
processes
=
6
)
...
...
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