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watcag-public
fpga-syspart
Commits
6bc1f282
Commit
6bc1f282
authored
Jun 01, 2020
by
LongChan
Browse files
correct scale
parent
b8063fa5
Changes
2
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2 changed files
with
15 additions
and
15 deletions
+15
-15
scaleSim/generate_square_data_set.sh
scaleSim/generate_square_data_set.sh
+2
-2
scaleSim/scale.py
scaleSim/scale.py
+13
-13
No files found.
scaleSim/generate_square_data_set.sh
View file @
6bc1f282
#!/bin/bash
# ./generate_square_data_set.sh configs/US_sim.cfg topologies/
960_DNN/Alexnet.csv
# ./generate_square_data_set.sh configs/US_sim.cfg
../
topologies/
mlperf/AlphaGoZero.csv 51840
if
[
"
$1
"
!=
""
]
;
then
python3 scale.py
-arch_config
=
$1
-network
=
$2
-ultraScale
=
False
-enable_mp
=
True
-custom_mem_size
=
True
-res_unit_limit
=
$3
else
echo
"Positional parameter 1 is empty"
fi
\ No newline at end of file
fi
scaleSim/scale.py
View file @
6bc1f282
...
...
@@ -262,24 +262,24 @@ class scale:
self
.
dataflow
=
'ws'
net_name
=
self
.
topology_file
.
split
(
'/'
)[
-
1
].
split
(
'.'
)[
0
]
all_arr_dim_list
=
[
(
18
,
18
),(
21
,
21
)
]
#
if self.square_res_limit != 0:
#
# 9024 / 3 = 3008
#
for k in range(1, 3009):
#
for i in range(1, 1920):
#
# for i in range(1, int(3008 / (k * 3))):
#
if self.res_enough((k * 3, i)):
#
all_arr_dim_list.append((k * 3, i))
#
else:
#
for i in range(1920):
#
all_arr_dim_list.append((9, i+1))
all_arr_dim_list
=
[]
if
self
.
square_res_limit
!=
0
:
# 9024 / 3 = 3008
for
k
in
range
(
1
,
3009
):
for
i
in
range
(
1
,
1920
):
# for i in range(1, int(3008 / (k * 3))):
if
self
.
res_enough
((
k
*
3
,
i
)):
all_arr_dim_list
.
append
((
k
*
3
,
i
))
else
:
for
i
in
range
(
1920
):
all_arr_dim_list
.
append
((
9
,
i
+
1
))
print
(
len
(
all_arr_dim_list
))
print
(
all_arr_dim_list
)
pool
=
Pool
(
processes
=
6
)
pool
=
Pool
(
processes
=
8
)
for
pro
in
pool
.
imap_unordered
(
self
.
run_mp_once
,
all_arr_dim_list
):
self
.
run_name
=
net_name
+
"_"
+
self
.
dataflow
+
"_"
+
str
(
pro
[
0
])
+
"x"
+
str
(
pro
[
1
])
self
.
cleanup
(
pro
)
...
...
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