Updated ezpc.h for logical and arithmetic right shifts: arithmetic right shift...

Updated ezpc.h for logical and arithmetic right shifts: arithmetic right shift now uses logical as subroutine; logical was earlier not padding the output shares correctly - fixed that.

EzPC/ABY_example/common/ezpc.h

@@ -45,13 +45,6 @@ share* left_shift(Circuit* c, share* val, uint32_t shift_factor) {
   return fresh_zero_share;
 }
 
-share* logical_right_shift(Circuit* c, share* val, uint32_t shift_factor) {
-  vector<uint32_t> tmp = val->get_wires();
-  tmp.erase(tmp.begin(), tmp.begin() + shift_factor);
-  // tmp.insert(tmp.end(), shift_factor, 0);
-  return create_new_share( tmp , c );
-}
-
 share* get_zero_share(Circuit* c, int bitlen){
   if (bitlen == 32)
     return put_cons32_gate(c, 0);
@@ -59,11 +52,8 @@ share* get_zero_share(Circuit* c, int bitlen){
     return put_cons64_gate(c, 0);
 }
 
-share* arithmetic_right_shift(Circuit* c, share* val, uint32_t shift_factor) {
-  int bitlen = (val->get_wires()).size();
-  share* neg_val = c->PutSUBGate(get_zero_share(c, bitlen), val);
-  share* is_pos = c->PutGTGate(neg_val, val);
-  val = c->PutMUXGate(val, neg_val, is_pos);
+share* logical_right_shift(Circuit* c, share* val, uint32_t shift_factor) {
+  int bitlen = val->get_bitlength();
   vector<uint32_t> val_wires = val->get_wires();
 
   vector<uint32_t> zero_share_wires = (get_zero_share(c, bitlen))->get_wires();
@@ -77,6 +67,15 @@ share* arithmetic_right_shift(Circuit* c, share* val, uint32_t shift_factor) {
     }
   }
   share* x = create_new_share(new_val_wires, c);
+  return x;
+}
+
+share* arithmetic_right_shift(Circuit* c, share* val, uint32_t shift_factor) {
+  int bitlen = val->get_bitlength();
+  share* neg_val = c->PutSUBGate(get_zero_share(c, bitlen), val);
+  share* is_pos = c->PutGTGate(neg_val, val);
+  val = c->PutMUXGate(val, neg_val, is_pos);
+  share* x = logical_right_shift(c, val, shift_factor);
   return c->PutMUXGate(x, c->PutSUBGate(get_zero_share(c, bitlen), x), is_pos);
 }